Murr Elektronik MVK-MPNIO DIO8 (DIO8) Part No. Murr 55289 Murr bus module distribution

Murr 55289 bus module is the public communication backbone for transmitting information between various functional components of a computer. It is a transmission bundle composed of wires. According to the types of information transmitted by the computer, computer buses can be divided into data buses, address buses, and control buses, used respectively for transmitting data, data addresses, and control signals. A bus is an internal structure; it is the common channel for information transfer between the cpu, memory, input, and output devices. The various components of the host are connected via the bus, and external devices are connected to the bus through corresponding interface circuits, thereby forming the computer hardware system. In a computer system, the public path for transmitting information between components is called the bus. Microcomputers connect various functional components using a bus structure. In this bus topology network structure, all devices are directly connected to the bus. The medium used is generally coaxial cable (including thick and thin cables), although optical fiber is now also used as a bus-type transmission medium. For example, the ATM network and networks using Cable Modem belong to bus-type network structures. Bus module

Murr 55289 bus module features

1. The dual-bus structure oriented toward memory has high information transmission efficiency, which is its main advantage. However, conflicts still occur when the CPU and I/O interfaces both need to access memory. 2. The CPU connects to high-speed local memory and local I/O interfaces via a high-transmission-rate local bus, while slower global memory and global I/O interfaces connect to a slower global bus. This balances high-speed and slow-speed devices, preventing mutual interference. 3. Simplifies hardware design. It facilitates modular structural design methods. Microcomputer designs oriented toward the bus only require making cpu plug-ins, memory plug-ins, and I/O plug-ins according to these specifications. Connecting them to the bus allows them to operate without considering the detailed operations of the bus. 4. Simplifies system structure. The entire system structure is clear. There are fewer connections, and backplane wiring can be printed. 5. Good system expandability. First, scale expansion merely requires inserting more plug-ins of the same type. Second, function expansion merely requires designing new plug-ins according to bus standards. The insertion positions for plug-ins in the machine often have no strict limits. 6. Good system update performance. Because the cpu, memory, I/O interfaces, etc., are connected to the bus according to bus protocols, as long as the bus design is appropriate, new plug-ins can be designed at any time following advances in processor chips and other related chips. Inserting new plug-ins into the backplane updates the system, and other plug-ins and backplane wiring generally do not need modification. 14. Facilitates fault diagnosis and maintenance. Motherboard test cards can conveniently locate faulty parts and identify the bus type.

Murr 55289 bus module classification

Common data buses include ISA (ISA bus), EISA, VESA, PCI, etc. "Address bus AB" is dedicated to transmitting addresses. Since addresses can only be transmitted from the CPU to external memory or I/O ports, the address bus is always unidirectional and tri-state, unlike the data bus. The bit width of the address bus determines the size of the memory space that the CPU can directly address. For example, if an 8-bit microcomputer has an 16-bit address bus, its maximum addressable space is 2^16=64KB. An 16-bit microcomputer (x-bit processor refers to the number of bits (1, 0) the microprocessor can process in one clock cycle, i.e., the word size) has an 20-bit address bus, and its addressable space is 2^20=1MB. Generally, if the address bus is n bits, the addressable space is 2^n bytes. "Control bus CB" is used to transmit control signals and timing signals. Among control signals, some are sent by the microprocessor to memory and I/O interface circuits, such as read/write signals, chip select signals, and interrupt response signals. Others are fed back to the CPU by other components, such as interrupt request signals, reset signals, bus request signals, and device ready signals. Therefore, the transmission direction of the control bus depends on the specific control signal; (information) is generally bidirectional. The bit width of the control bus depends on the actual control needs of the system. In practice, the specific situation of the control bus mainly depends on the CPU. Classified by data transmission method, buses can be divided into serial buses and parallel buses. In serial buses, binary data is sent bit by bit to the destination device via a single data line. Parallel buses typically have more than 2 data lines. Common serial buses include SPI, I2C, USB, and RS232. Classified by whether the clock signal is independent, buses can be divided into synchronous and asynchronous buses. The clock signal of a synchronous bus is independent of the data, whereas the clock signal of an asynchronous bus is extracted from the data. SPI and I2C are synchronous serial buses, while RS232 uses an asynchronous serial bus.

Murr 55289 bus module operation

A bus operation completes the transmission of information between two modules. The master module initiates the operation, and the other is the slave module. At any given moment, only one master module can occupy the bus. Bus operation steps: The master module requests bus control, and the bus controller makes the arbitration. Bus operation steps: After obtaining bus control, the master module addresses the slave module, and data transmission occurs after confirmation by the slave module. Error checking for data transmission. Bus timing protocols: Timing protocols ensure synchronized operation and correct transmission between both parties. There are three types of timing protocols: Synchronous bus timing: All modules on the bus share the same clock pulse for operation control. All actions of each module occur at the start of a clock cycle, and most actions are completed within one clock cycle. Asynchronous bus timing: The occurrence of an operation is determined by specific signals from the source or destination module. The occurrence of an event on the bus depends on the previous event, with both parties providing handshake signals. Semi-synchronous bus timing: The time intervals between operations on the bus can vary but must be integer multiples of the clock cycle. Signal appearance, sampling, and termination are still based on the common clock. ISA bus uses this timing method. Data transmission types: Divided into single-cycle mode and burst (burst) mode. Single-cycle mode: Only one data item is transmitted per bus cycle. Burst mode: Multiple data items are transmitted after obtaining master line control. Addressing is provided during addressing.

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